Senior DFT Engineer
 Microsoft | |
 United States, North Carolina, Raleigh | |
 Jul 23, 2025 | |
|
OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. We are looking for a Senior DFT Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
ResponsibilitiesAs a Senior Engineer, DFT in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our projects. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. In this high impact & highly visible role on the team, you will be responsible for: The design, implementation and testing of computer hardware products that add strategic value to the company Specifically, design and develop scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT features on the ATE. Improve the design, development, and overall quality of the hardware products and development processes. Work on memory BIST design optimization to make sure design is time and area efficient. Collaborate on a regular basis with memory unit owners for DFT architecture and flow development. Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects. Develop ATE test patterns and algorithms to cover various memory and scan fault models. Work on infrastructure and test flow development for unit level and full chip verification. Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion and testing. Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project. Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. Justify and show ROI for BIST and logic redundancy. Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement. | |