New

Design for Test Engineer - Early Career

Marvell Semiconductor, Inc.
United States, Massachusetts, Westborough
Apr 16, 2026
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Design for Test (DFT) Engineer supports the development and implementation of testability features in digital integrated circuits to ensure high product quality and manufacturability. This role is ideal for recent graduates or earlycareer engineers interested in VLSI design, silicon validation, and semiconductor manufacturing flows. What You Can Expect Assist in implementing DFT structures such as scan chains, boundary scan (JTAG), and BuiltIn SelfTest (BIST) Support scan insertion and verification using industrystandard EDA tools Generate scripts that support automation of DFT flows Collaborate with design, verification, and physical design teams to ensure testability requirements are met Help analyze test coverage metrics (e.g., stuckat, transition, path delay faults) Identify and assist in debugging DFTrelated issues during simulation, synthesis, and postsilicon testing Contribute to documentation of DFT methodologies, guidelines, and test results Learn and follow company design and test best practices What We're Looking For Required Qualifications Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with 1- 2 years of related experience OR a Master's Degree in Electrical Engineering, Computer Engineering, or a related field Basic understanding of digital logic design and computer architecture Familiarity with DFT concepts, such as: scan chains, ATPG (Automatic Test Pattern Generation), and fault models Exposure to HDL languages (Verilog or VHDL) Fundamental knowledge of ASIC or SoC design flow Strong attention to detail, analytical and problemsolving skills Ability to work collaboratively in a team environment Preferred Qualifications Academic or internship experience in semiconductor design or testing Basic scripting knowledge (Python, Tcl, or Shell) Familiarity with EDA tools Understanding of manufacturing test flows and yield analysis Exposure to lowpower or highspeed design considerations Expected Base Pay Range (USD) 108,500 - 160,510, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TT1