Principal AI Compiler Engineer

About this opportunity:

Principal AI Model Architect, Austin, Texas

This is not a remote work opportunity

The Rarest Role in 5G Silicon. Built for the Rarest Kind of Engineer.
The Mission
Most AI runs on someone else's hardware. You're going to design the hardware around the AI.

As the Principal AI Model Architect, you sit at the most critical intersection in our entire silicon program - the place where bleeding-edge AI research collides with custom ASIC reality. You are the "Voice of the Model" - the person who takes ambitious algorithms born in a research lab and answers the hardest question in the building:

"How do we actually run this on silicon we haven't built yet - and make it faster than anyone else on the planet?"

You won't just map models to hardware. You'll shatter them - strategically, surgically - across a heterogeneous ASIC architecture purpose-built for the demands of next-generation 5G AI. Your decisions will be etched into silicon. Your projections will determine tape-out confidence. Your golden models will be the source of truth that an entire SDK team builds against.

This is not a support role. This is the role that makes the chip worth building.

What You'll Own
The Hardware-Software Bridge
You are the translator between two worlds that rarely speak the same language. You'll take complex AI and RAN algorithms - Transformers, Grouped Query Attention, Positional Embeddings - and forge them into concrete hardware specifications for the ASIC team and precise lowering requirements for the SDK team. When there's ambiguity between what research wants and what silicon can deliver, you resolve it.

Model Partitioning & Tiling Strategy
Massive parameter models don't fit neatly onto a chip. You'll define exactly how they do - determining the partitioning, tiling, and memory staging strategies that make heterogeneous execution not just possible, but optimal. This is where deep theoretical knowledge meets brutal real-world constraint, and where the best architects separate themselves from everyone else.

Golden Model Ownership
You maintain the Source of Truth - reference implementations in JAX/PyTorch that capture the researcher's intent with zero ambiguity. You'll work shoulder-to-shoulder with the SDK team to ensure that what comes out of the MLIR compiler is exactly what went into the model. 100% fidelity. No exceptions.

Cycle-Accurate Performance Projection
Before a single gate is synthesized, you'll use your architectural intuition and simulation expertise to project exactly how next-generation silicon targets will perform. Your numbers will drive investment decisions, microarchitecture tradeoffs, and tape-out timelines. You're not guessing - you're proving it before it exists.

What You Bring
Model Architecture Mastery
You have deep, battle-tested knowledge of Transformer architectures, modern attention mechanisms (GQA, MQA), and embedding strategies - not just how they work, but why they work, and exactly where they break under hardware constraints.

Hardware-Aware ML - For Real
You've done Hardware-in-the-Loop research. You think about cache lines, memory walls, HBM vs. SRAM bandwidth ceilings, and SIMD/VLIW execution units while you design models - not after. The memory wall isn't a problem you hand off. It's a design constraint you architect around.

Framework Mastery at the Metal
Advanced proficiency in JAX (strongly preferred), PyTorch, or TensorFlow - specifically in model export, graph capture, and the XLA/StableHLO stack. You know what happens to a model between Python and an execution kernel, and you can control it.

Performance Modeling Depth
Experience with SystemC, TLM, or custom cycle-accurate simulators. You validate performance before tape-out - because after is too late and too expensive.

The Profile That Makes Us Stop Scrolling
Telecom DNA: You've applied AI to real RAN workloads - beamforming, channel estimation, L1/L2/L3 signal processing. You understand that 5G AI is not the same as data center AI.
Compiler Fluency: You don't need to write MLIR passes from scratch - but you absolutely know the difference between a high-level computation graph and a linearized execution schedule, and you can have an intelligent conversation about what happens in between.
Numeric Instinct: You've worked with complex-number representations in AI models and understand how they map to specialized DSP and matrix hardware. You know why this matters and where it breaks.
Why This Role. Why Now.
Ericsson Silicon is building custom ASICs at the most advanced technology nodes available - purpose-engineered to run AI at the edge of a global 5G network. The scale is real. The stakes are real. The team is world-class.

This is the kind of role that defines a career - the rare opportunity to have your architectural decisions running inside infrastructure that connects billions of people.

If this is the role you've been waiting for, we want to hear from you.